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Job ID: 149242443
Skills:
Regression Analysis, Cadence Xcelium, Top-Level Verification, wreal Modeling, model validation, Cadence VIVA, Schematic-Level Correlation, Uvm, Coverage-Driven Verification, Analog Circuit Fundamentals, Waveform Debug, SV-RNM, Verification Planning, Cadence ADE Assembler, Simulation Debug, SoC AMS Verification, Digital Design Flow, Mixed-Signal SoC Integration, systemverilog, Verilog-AMS, Cadence SimVision, Cadence Virtuoso, AMS Verification Methodology, Mixed-Signal Verification
Skills:
.NET, Test Automation, Python, System Verification
Skills:
code coverage , C, Shell, Perl, Verilog, System Verilog, Python, Tcl, Metric Driven Verification, Uvm, formal verification methodologies, assertions, functional coverage, constrained random methodologies
Skills:
Verilog, System Verilog, CPU architecture, Coherent fabric designs, debugging skills, ARM knowledge
Skills:
Perl, Shell scripting, Python, UVM Universal Verification Methodology, PCIe protocol, Debugging RTL and gate level simulation issues, systemverilog
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