Regression Analysis, Cadence Xcelium, Top-Level Verification, wreal Modeling, model validation, Cadence VIVA, Schematic-Level Correlation, Uvm, Coverage-Driven Verification, Analog Circuit Fundamentals, Waveform Debug, SV-RNM, Verification Planning, Cadence ADE Assembler, Simulation Debug, SoC AMS Verification, Digital Design Flow, Mixed-Signal SoC Integration, systemverilog, Verilog-AMS, Cadence SimVision, Cadence Virtuoso, AMS Verification Methodology, Mixed-Signal Verification

.NET, Test Automation, Python, System Verification

code coverage , C, Shell, Perl, Verilog, System Verilog, Python, Tcl, Metric Driven Verification, Uvm, formal verification methodologies, assertions, functional coverage, constrained random methodologies

Verilog, System Verilog, CPU architecture, Coherent fabric designs, debugging skills, ARM knowledge

Perl, Shell scripting, Python, UVM Universal Verification Methodology, PCIe protocol, Debugging RTL and gate level simulation issues, systemverilog

code coverage , Fpga, Ovm, Test Cases, Hdl, Shell, Pcie, Verilog, Debugging, System Verilog, Python, Perl, Pci, Sta, test benches, RTL, Uvm, DDR PHY, Ethernet MAC, VHDL, ASIC, RTL top level integration, Functional coverage, Frontend Design, Logic Synthesis, HVL

Verilog, VMM, assertion-based verification, Uvm, functional coverage, advanced verification methodologies, systemverilog

Perl, Pcie, Ethernet, Shell scripting, Python, CHI, Ace, USB 3.x, RISC-V, Uvm, Assertions, systemverilog, Axi, USB4, CXL, DDR5, DDR4, SVA