We are looking for an experienced Physical Design Engineer responsible for complete physical design and implementation, including floor planning, P&R, timing closure, power and noise analysis, and back-end verification across multiple advanced node projects.
Key Responsibilities:
- Perform chip floor planning, power/clock distribution, P&R, and chip assembly
- Achieve timing closure and conduct power/noise analysis
- Manage complete netlist to GDSII flow for ASIC designs
- Handle synthesis, STA, and physical implementation of hard-macros and/or full-chip designs
- Collaborate across teams to ensure successful backend design and delivery
- Utilize low-power design techniques and apply them effectively in backend flow
- Develop and maintain automation using scripting languages