Technical Architect

Technical Architect Design Verification

Location-Bengaluru/Hyderabad/Noida

Experience-10+yrs

Role Overview:

As a Technical Architect Design Verification, you will lead verification architecture, methodology, and execution for advanced, high-speed interface IPs such as PCIe Gen5/Gen6 and USB 3.0/3.1. You will collaborate with design, architecture, and physical teams to ensure verification completeness, mentor engineers, and influence organization-wide best practices.

Key Responsibilities

• Define and drive verification architecture, methodology, and test strategy for complex digital IPs and SoCs.
• Architect and develop UVM-based environments using SystemVerilog for scalable and reusable verification frameworks.
• Lead verification of PCIe Gen5/Gen6 and USB 3.0/3.1 IPs, including protocol-level and system-level components.
• Work closely with design, firmware, and validation teams to ensure functional correctness and performance compliance.
• Identify corner cases, build coverage plans, and achieve coverage closure and sign-off.
• Conduct debug, root cause analysis, and regression management using industry-leading EDA tools.
• Explore, evaluate, and deploy advanced DV methodologies like formal, emulation, or hybrid approaches.
• Mentor junior engineers and contribute to building a strong verification culture within Silicon Patterns.

Required Skills and Experience

• 10+ years of hands-on ASIC/SoC Design Verification experience.
• Strong proficiency in SystemVerilog and UVM methodologies.
• In-depth knowledge of PCIe Gen5/Gen6 and USB 3.0/3.1 protocols.
• Experience in constrained random verification, functional coverage, and VIP integration.
• Good understanding of simulation tools (VCS, Xcelium, QuestaSim, Verdi) and debug/trace analysis.
• Exposure to scripting (Python, Perl, or Tcl) for automation and flow enhancement.
• Excellent analytical, communication, and leadership skills.

Preferred Qualifications

• Familiarity with SoC-level verification, C-model integration, or co-emulation platforms.
• Understanding of Formal Verification or Portable Stimulus (PSS) flows.
• Track record of mentoring teams and driving verification initiatives at an organizational level.

Education

• B.E/B.Tech or M.E/M.Tech in Electronics, Electrical, or Computer Engineering.

About Us:

Silicon Patterns is a specialized engineering services company with deep expertise in pre-silicon and post-silicon design and verification. We deliver end-to-end semiconductor and embedded system solutions covering RTL Design, SystemC Modeling, Emulation, Design Verification (DV), Physical Design (PD), Design for Testability (DFT), and Pre- & Post-silicon Validation helping clients achieve faster, more reliable product development. Headquartered in Hyderabad, with offices in Bangalore and Raipur, and supported by our skilled engineering teams in Malaysia, we serve global clients through flexible engagement models like Time & Materials (T&M), Offshore Development Centers (ODC), Subcontracting, and Build-Operate-Transfer (BOT). Our expertise spans VLSI and Embedded Systems, with a strong focus on Wireless, IoT, and Automotive domains. We also work on advanced technologies including HBM3/3E workloads, AI/ML, GenAI/LLMs, and edge computing. At Silicon Patterns, we're committed not only to technical excellence but also to maintaining a strong work-life balance for our teams because great engineering starts with well-supported people.

Website

https://www.siliconpatterns.com