System-on-Chip Design Engineer
System-on-Chip Design Engineer
leadsoc technologies pvt ltdThis job is no longer accepting applications
Job Description
System-on-Chip (SoC) Design Engineer
Location: Bengaluru, India
Experience: 5–12 Years
Role:
Design and implement high-performance SoC subsystems from microarchitecture to silicon. Collaborate with architecture, verification, DFT, STA, and physical design teams to deliver high-quality, PPA-optimized RTL for next-generation AI, Compute, and Networking SoCs.
Responsibilities
- Develop microarchitecture and RTL using Verilog/SystemVerilog.
- Design datapaths, pipelines, FSMs, memory interfaces, and control logic.
- Integrate SoC IPs and AMBA-based interconnects (AXI/AHB/APB).
- Optimize designs for Power, Performance, and Area (PPA).
- Drive RTL quality through Lint, CDC/RDC, synthesis, and debug.
- Support timing closure, verification, and silicon bring-up.
Required Skills
- 5–12 years of ASIC/SoC RTL Design experience.
- Strong microarchitecture and RTL design expertise.
- Proficiency in Verilog/SystemVerilog and ARM-based SoC architecture.
- Experience with AMBA protocols, high-speed interfaces, and Synopsys Design Compiler.
- Hands-on with Lint, CDC/RDC, VCS/Xcelium/Questa, and Python/Tcl/Perl scripting.
- Exposure to advanced nodes (7nm/5nm/3nm) is a plus.
More Info
Job Type:
Industry:
Function:
Employment Type:
Key Skills
high-speed interfaces
ARM-based SoC architecture
Xcelium
AMBA protocols
RDC
Synopsys Design Compiler
About Company
Skills:
rtl development , Perl, Verilog, Python, Tcl, LINT, Synthesis, cdc, SOC design, NoC-based SoC architectures, structural checks, NoC microarchitecture, Timing, RTL quality signoff, ASIC SoC development flows, systemverilog, synthesizable RTL, spyglass, RDC
Skills:
Verilog, LINT, SDC constraints, cdc, UPF, systemverilog, Rtl Design, RDC, VCLP, Synthesis, SoC integration, Makefile-based flows, Low-power design concepts, Scripting in Tcl