Synthesis Engineer

Hiring: Synthesis Engineer

Location: Bengaluru

Experience: 3–7 Years

Notice Period: Immediate to 30 Days Preferred

Job Responsibilities

• Perform RTL-to-Gate synthesis for complex multi-million gate SoC designs.
• Drive physical-aware synthesis using Cadence Genus and/or Synopsys Fusion Compiler.
• Handle hierarchical and flat synthesis flows while achieving timing, area, power, and QoR targets.
• Debug synthesis issues across multi-clock domain designs and resolve timing violations.
• Perform multi-power domain synthesis and structural power checks using CLP.
• Execute Formal Verification (LEC) and debug equivalence issues.
• Collaborate with Physical Design, STA, DFT, and RTL teams for synthesis timing closure.
• Analyze and optimize timing, area, power, and congestion trade-offs.
• Develop and maintain synthesis constraints (SDC) and TCL automation scripts.

Required Skills

• Experience in handling complex multi-million gate synthesis.
• Hands-on experience with Cadence Genus and/or Synopsys Fusion Compiler.
• Strong understanding of physical-aware synthesis and timing closure.
• Experience with multi-clock and multi-power domain designs.
• Knowledge of CLP structural power checks and Formal Verification (LEC).
• Good understanding of STA concepts and interaction with PD and DFT teams.
• Strong TCL scripting, debugging, and problem-solving skills.
• Excellent communication and stakeholder management skills.

Education

• Bachelor's or Master's degree in Electronics & Communication Engineering (ECE), Electrical Engineering (EEE), Electronics & Instrumentation (E&I), VLSI Design, Microelectronics, or a related field.