rtl development , Clp, Tcl, Python, Perl, Memory BIST insertion, UPF development, Low power checks, Synopsys Prime Time, Synthesis LEC, Cadence Conformal Low Power, clock gating, Genus Fusion Compiler, RTL Lint, Physical Design, Cadence Conformal LEC, Synopsys DCG, Constraints validation, DRC, power optimization flows, TCL script development, Dft, MemBIST

Clp, Python, Tcl, Sta, Synopsys Cadence synthesis tools, LEC, RTL, UPF, Dft, Synthesis, SDC, MMMC, Physical Design, PPA Optimization

Tcl Scripting, SDC constraints, Timing Constraints, Fusion Compiler, Synopsys Design Compiler, clock gating, LEC, low-power design, UPF, ECO flows