Staff RTL Design Engineer

Exp Level : More than 5+Years will be considered

Company Description

NG-RAN IIT Hyderabad is at the forefront of global wireless innovation, prominently contributing to the development of 5G technologies. The institute's team, alongside academic and industry partners, submitted more than 400 technical papers to 3GPP workgroups from 2017 to 2021, resulting in several key contributions recognized as 5G standard-essential patents (SEPs). With funding from Indian government entities, IITH developed prototypes of groundbreaking technologies such as 5G base stations and NB-IoT System-on-Chip (SoC). These innovations have been commercialized by WiSig Networks, a start-up incubated at the institute. Looking ahead, IITH is committed to advancing global 6G standards, focusing on defining performance requirements and developing indigenous technologies for domestic and global deployment.

Role Description

This is a full-time on-site position for a Staff RTL Design Engineer, located in Hyderabad. The role involves designing, developing, and validating RTL (Register Transfer Level) modules for wireless communication systems. Responsibilities include collaborating with cross-functional teams, analyzing design specifications, performing simulations, and optimizing designs for efficient implementation. The engineer will also provide technical expertise in system-level integration and troubleshooting during the product development cycle.

Job Location: IHyderabad,

Responsibilities:

Architecture exploration and Micro-architecture development

RTL design and integration for 5G NR UE systems using Verilog/System Verilog

Collaboration with multi-discipline teams to integrate, test and debug the designs on FPGAs

Skills/Experience Required

Strong Domain Knowledge on RTL Design, implementation, and integration for FPGA based designs.

Knowledge with RTL coding using Verilog/System Verilog.

Proficiency in complete FPGA design flow.

Experience with protocols like AXI4-stream and AXI4.

Exposure in scripting (Python/TCL).

Strong debugging capabilities at RTL simulation and FPGA Emulation.

Define micro-architecture and write detailed design specifications.

Develop RTL code based on system-level specifications using Verilog, VHDL, or SystemVerilog.

Implement complex digital functions and algorithms in RTL.

Create and execute detailed test plans to verify RTL designs.

Experience in implementing DSP algorithms

Knowledge with RTL design using Verilog/System Verilog and microarchitecture

Required Qualifications:

Master's/Bachelor's degree in Electrical/Electronics Engineering, Computer Engineering, or equivalent practical experience

Preferred Experience

Experience with Intel or Xilinx FPGAs especially MPSoC FPGAs

Experience in Fixed-point arithmetic implementation in Verilog

Experience with High speed serial communication IPs on FPGAs