Staff Engineer
Staff Engineer
Arm8-10 Years
This job is no longer accepting applications
Job Description
Job Overview
As a Staff Engineer in Arm's Solutions Engineering group we like to think we are not just crafting sophisticated SoCs, but we are defining future chip design techniques. Not only do we improve the power, performance and system integration of our products, but we also craft the design flows, influence Electronic Design Automation (EDA) tools and build the knowledge base that makes custom SoC and CPU chip design possible. At Arm, our work goes beyond multiple divisions where we drive improved implementation for Arm and our partners. A key component of this is around the development of comprehensive implementation and analysis methodologies.
Responsibilities
At Arm, we are guided by our core beliefs that reflect our creative culture and guide our decisions, defining how we work together to surpass ordinary and shape extraordinary.
As a Staff Engineer in Arm's Solutions Engineering group we like to think we are not just crafting sophisticated SoCs, but we are defining future chip design techniques. Not only do we improve the power, performance and system integration of our products, but we also craft the design flows, influence Electronic Design Automation (EDA) tools and build the knowledge base that makes custom SoC and CPU chip design possible. At Arm, our work goes beyond multiple divisions where we drive improved implementation for Arm and our partners. A key component of this is around the development of comprehensive implementation and analysis methodologies.
Responsibilities
- Synthesis, Physical design and implementation of CPU cores, system interconnect and other ARM IP
- Analyze design timing, area and power to help improve the quality of ARM IP
- Develop and deploy new methodologies to improve implementation efficiency and results
- Support and develop detailed implementation analysis and data-mining methodologies.
- Work with implementation and physical IP RTL design teams to drive analysis and optimization of our IP.
- Converting R&D concepts into real implementation solutions.
- Enable our partners to achieve the best possible quality of results.
- Bachelors or Master's degree equivalent in Electrical Engineering, Computer Engineering or other relevant technical fields.
- 8+ years of proven experience in ASIC Implementation, Physical design, STA and Timing closure, Structured clock tree, PDN analysis, DFM and Physical verification
- The ability to demonstrate that you can express new insights and communicate them effectively.
- Possess a high level of dedicated, initiative and problem-solving skills.
- Experience in crafting and adopting new silicon implementation techniques and methodologies and promote their use with international teams
- Previous experience in and knowledge of the entire IC design flow, from RTL through to GDS2.
- Experience working closely in top and block level Synthesis, Floor planning, Place and Route, CTS, logical and physical optimization, timing closure and power analysis flows.
- Proven programming and scripting skills eg. Tcl, Perl, R, Make.
- Knowledge around Arm based SoCs!
- Experience with a wide range of programming, scripting & data presentation languages Eg. Tcl, sh, csh, make, R, C, C++, Java, JS, HTML, Perl, Python, Ruby.
- Experience with low power design techniques (power gating, voltage/frequency scaling)
- Experience with Verilog RTL design.
- Experience with ATPG tools/and or production testing.
At Arm, we are guided by our core beliefs that reflect our creative culture and guide our decisions, defining how we work together to surpass ordinary and shape extraordinary.
More Info
Job Type:
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Key Skills
Logical and physical optimization
PDN analysis
CTS
ASIC Implementation
Structured clock tree
About Company
Skills:
Uncore subsystems, Physical Design, FinFET nodes, EDA suites, Cadence, Synopsys, RTL-to-GDSII
Skills:
synopsys primetime , timing closure and sign-off, clocking architecture and CDC concepts, Physical Design flow, advanced technology nodes
Skills:
Ovm, Spi, Soc Architecture, Verilog, I2c, System Verilog, Python, Usb, Perl, Ethernet, Arm, Tcl, Bus Matrix design, MIPS, DFT concepts, Uvm, Rtl Design, Synthesis, RDC, Power estimations, Timing constraint SDC, ASIC design flow, LINT, Formal CDC, MBIST, Axi, AMBA, BUS Protocols, Low-power design, Timing Analysis, peripheral IPs
Skills:
Rtl Design, Synthesis, RISC CPU IP, Emulation, silicon bring-up, Microarchitecture, Verification, Timing Analysis, Physical Design, SoC design methodology
Skills:
Physical Verification (PV), Power Switch Estimation, Package Co-design, Power Grid Design, ESD and Reliability Sign-off, Industry-standard Physical Verification and Power Grid Sign-off tools, Static and Dynamic EM IR Analysis, Physical Design, Timing Closure, I/O Planning, WireBond and FlipChip packaging methodologies