Uncore subsystems, Physical Design, FinFET nodes, EDA suites, Cadence, Synopsys, RTL-to-GDSII

synopsys primetime , timing closure and sign-off, clocking architecture and CDC concepts, Physical Design flow, advanced technology nodes

Ovm, Spi, Soc Architecture, Verilog, I2c, System Verilog, Python, Usb, Perl, Ethernet, Arm, Tcl, Bus Matrix design, MIPS, DFT concepts, Uvm, Rtl Design, Synthesis, RDC, Power estimations, Timing constraint SDC, ASIC design flow, LINT, Formal CDC, MBIST, Axi, AMBA, BUS Protocols, Low-power design, Timing Analysis, peripheral IPs

Rtl Design, Synthesis, RISC CPU IP, Emulation, silicon bring-up, Microarchitecture, Verification, Timing Analysis, Physical Design, SoC design methodology

Physical Verification (PV), Power Switch Estimation, Package Co-design, Power Grid Design, ESD and Reliability Sign-off, Industry-standard Physical Verification and Power Grid Sign-off tools, Static and Dynamic EM IR Analysis, Physical Design, Timing Closure, I/O Planning, WireBond and FlipChip packaging methodologies

Perl, Python, Tcl, Timing Closure STA, RTL-to-GDSII Execution, Red Hawk, Programming Scripting, Fusion Compiler, LEC, Tempus, Cross-Functional Collaboration, Physical Formal Verification, Innovus, Calibre, primetime, PPA Optimization, EDA Tools, VCLP