Staff Design Engineer

Aeva

10-12 Years

Bengaluru, India

Posted 2 months ago
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Job Description

Role Summary:

As a key player on the Digital Design team, you will participate in the RTL design and development of the signal processing path for Aeva's 4-D Lidar processing chip. You will be responsible for implementing and/or integrating sub-components of the design in ASICs and FPGAs.

What you'll be doing:
Develop custom sub-components of the digital signaling pipeline like filters, FFTs, control logic, etc
Write micro-architecture specifications, Code RTL, Test & Validate Aeva-specific sub-components
Implement additional functionality including functional safety and robustness functions
Focus on developing efficient, highly reliable, highly available, robust functionality
Work with Architects, design engineers, verification engineers, and System software teams to ensure that the SOC meets its functional, performance, and power targets
What you'll have:
10+ years of experience in the design of DSP designs, algorithms, and signal processing functionality in ASICs/FPGAs. Ability to achieve high performance and low power targets
Experience writing System Verilog RTL Code
Working experience and knowledge in AMBA protocols
Desire to learn & implement groundbreaking new processes and methodology for continuous improvement
Nice to haves:
Matlab/NumPy/C/C++
Working experience and knowledge in LPDDR, Ethernet, MIPI, and high-speed Serdes etc
Experience in FPGA designs, pre-silicon validation on emulation platforms such as Cadence Palladium, Mentor Veloce, Synopsys Zebu
Post-silicon bring-up and validation planning and execution
Diagnostics Firmware development and validation

More Info

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About Company

Aeva

Job ID: 141181041

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Last Updated: 01-09-2026 01:48:32 AM

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