C, Pcie, Ethernet, SV, CXL, UCIe, Uvm, systemverilog

static timing analysis, Synthesis, RISC CPU IP, ARM CPUs, Emulation, chip validation, Timing Analysis, CPU microarchitecture, SoC design methodology, Physical Design, IP integration, CDC analysis, Rtl Design, Floor Planning, linting, BUS Protocols, Timing Closure, characterisation, silicon bring-up, Verification, equivalence checking

C, Clearcase, Cryptography, Aes, Encryption, Clearquest, Perl, Verilog, Python, System Verilog, LINT, cdc, RTL design using Verilog, hash functions, GMAC, signatures, LEC, SHA, private key, ASIC development tools, random number generator

DDR, Usb, Pcie, Ethernet, SPICE-based simulators, MIPI, Hspice, ESD architecture, LPDDR, ESD circuit design, Spectre

Ovm, Spi, Soc Architecture, Verilog, I2c, System Verilog, Python, Usb, Perl, Ethernet, Arm, Tcl, Bus Matrix design, MIPS, DFT concepts, Uvm, Rtl Design, Synthesis, RDC, Power estimations, Timing constraint SDC, ASIC design flow, LINT, Formal CDC, MBIST, Axi, AMBA, BUS Protocols, Low-power design, Timing Analysis, peripheral IPs

Schematic design, MATLAB, Python, Synopsys Custom Compiler, BERTs, Spectre, Hspice, Cadence Virtuoso, Layout interaction, behavioral modeling, Lab measurements, BER estimation, High-speed oscilloscopes, Post-layout verification, Design sign-off, Jitter budgeting, Parasitic Extraction, Silicon bring-up