Hands on experience with Synthesizable Verilog/ System Verilog RTL coding for ASIC designs and Simulation tools
Lint, CDC, Synthesis flow and static timing flows, Formal checking, etc is a must for candidates with design background
Experience with high speed design greater than 600MHz and with P&R aware synthesis including usage of tools such as Fusion Compiler is a significant plus
Experience with Perforce or similar revision control environment
Knowledge of Perl/Shell scripts
Exposure to quality processes in the context of IP design and verification is an added advantage
Ability to work/ Prior experience as a Technical Lead for a small team is a major plus
Should be able to mentor and technically lead a team of designers
In addition, the candidate should have good communication skills, should be a team player and possess good problem solving skills and show high levels of initiative
