We are looking for an experienced and highly skilled Physical Design Engineer to join our Enterprise SSD Group. The selected candidate will contribute to the physical implementation of complex processors, controller architectures, and ASICs used in high-performance enterprise storage solutions. This role demands strong expertise in advanced-node physical design, block-level implementation, timing closure, and physical verification.
The engineer will play a critical role in delivering high-quality silicon by ensuring power, performance, and area (PPA) goals are met while maintaining design robustness and manufacturability. The position requires close collaboration with RTL, DFT, STA, and verification teams to ensure seamless tape-out execution.
Key Responsibilities
- Perform block-level physical design implementation including floorplanning, placement, clock tree synthesis (CTS), routing, and optimization.
- Develop and enhance APR (Automatic Place and Route) flows for improved efficiency and repeatability.
- Execute low-power-aware floorplanning and implementation strategies aligned with power intent specifications.
- Conduct RC extraction and Static Timing Analysis (STA) to achieve timing closure at block level.
- Drive PPA (Power, Performance, Area) analysis and optimization across design iterations.
- Perform and close physical verification checks including DRC, LVS, ERC, and antenna violations using industry-standard tools.
- Work on IR drop and Electromigration (EM) analysis and resolve issues based on sign-off feedback.
- Ensure complete closure of IR violations within the block and maintain design integrity across corners and modes.
- Participate actively in tape-out activities and ensure all sign-off criteria are met.
- Collaborate with cross-functional teams to resolve implementation challenges and meet aggressive project timelines.
- Support continuous improvement initiatives for design methodology and tool flows.
Required Skills And Qualifications
- 58 years of hands-on experience in physical design implementation for ASICs or SoCs.
- Strong experience in block-level STA timing closure across multiple modes and corners.
- Proven experience working in advanced process technology nodes (6nm/7nm preferred).
- Expertise in Cadence physical design tools such as Innovus and Tempus.
- Hands-on experience with physical verification closure (DRC, LVS, Antenna checks) using Calibre tool suite.
- Experience in IR drop and EM analysis and successful closure of related issues.
- Strong knowledge of APR flow development and optimization techniques.
- Solid understanding of digital electronics fundamentals and microprocessor architecture.
- Excellent analytical and debugging skills with strong attention to detail.
- Ability to manage multiple tasks and meet project deadlines effectively.
- Strong ownership mindset, accountability, and commitment to high-quality deliverables.
- Good written and verbal communication skills in English.
- Strong interpersonal skills and ability to collaborate effectively within cross-functional teams.
- Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering, or related discipline.
Preferred Skills
- Strong verbal communication and presentation skills.
- Deep expertise in Cadence Place-and-Route (PnR) tools.
- Exposure to formal verification methodologies.
- Experience working on digital electronics and microprocessor-based designs.
- Familiarity with power intent formats (UPF/CPF) and low-power design methodologies.
- Experience working in high-performance storage or processor-based product environments.
Ideal Candidate Profile
The ideal candidate is technically strong in advanced-node physical implementation and thrives in fast-paced, high-performance design environments. They should demonstrate strong problem-solving abilities, the capability to analyze complex design challenges, and a proactive approach toward achieving closure across all sign-off parameters. A collaborative mindset, clear communication, and dedication to delivering silicon-ready designs are critical for success in this role.
Skills: microprocessors,physical design implementatio,physical design,sta,clock tree synthesis,apr flow development,ir/em analysis,ppa analysis,drc/lvs/erc,sta timing closure
