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STA Engineer
Mirafra Technologies

STA Engineer

Mirafra Technologies
3-5 Years
Not Disclosed

This job is no longer accepting applications

Job Description

JD

STA, Timing Closure is must

Veena Johar is looking for profiles, with some PD experience, like Placement and Routing (PnR), Static Timing Analysis (STA) along with TCL scripting with 3+ years of experience along with FPGA Design.

• BS or MS in EE or CE with 3+ years of experience in digital design and/or timing closure.

• Strong background in RTL design using Verilog/VHDL.

• Timing Constraints (SDC) & Static Timing Analysis .

• Strong understanding and usage of ASIC and/or FPGA software tool

chain like Vivado or Quartus.

• Strong Digital Design Fundamentals and applications

• TCL Scripting language

  • • Applications and Designs in Wireless/Wired domain.ior experience in STA or physical design in the semiconductor industry preferred.
  • Experience with advanced technology nodes, multi-mode multi-corner analysis, ECO flows, and timing sign-off for high-performance or low-power designs is beneficial.

Location- Bangalore, Hyderabad and Noida

Share resume to [Confidential Information]

Exp-3+ years

More Info

Job Type:
Permanent Job
Industry:
Semiconductor Manufacturing
Function:
Semiconductor
Employment Type:
Full time

Key Skills

RTL design using Verilog

Timing Constraints SDC

Digital Design Fundamentals

Tcl Scripting
FPGA Design
Last Updated: 13-10-2026 06:29:27 PM

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