Job Title: Static Timing Analysis (STA) Engineer
Experience: 5+ Years
Location: Bengaluru
Employment Type: Full-time
Job Summary
We are looking for a skilled STA Engineer to join our VLSI Physical Design team. The candidate will be responsible for performing Static Timing Analysis, timing closure, and timing signoff for advanced technology nodes.
Key Responsibilities
- Perform Static Timing Analysis (STA) for block and full-chip level designs.
- Work on timing closure across all corners and modes.
- Analyze and fix setup, hold, transition, and capacitance violations.
- Collaborate with Physical Design, Synthesis, and RTL teams to resolve timing issues.
- Perform timing signoff using industry-standard tools.
- Debug and resolve timing issues in post-synthesis and post-layout stages.
- Work on timing constraints (SDC) creation and validation.
- Support ECO implementation for timing fixes.
Required Skills
- Strong knowledge of Static Timing Analysis concepts.
- Experience with PrimeTime, Tempus, or equivalent STA tools.
- Understanding of timing constraints, clock tree, and timing closure techniques.
- Familiarity with Synthesis and Physical Design flow.
- Good knowledge of advanced nodes (7nm, 5nm, etc.) is a plus.
- Experience with MCMM (Multi-Corner Multi-Mode) analysis.
- Scripting knowledge in TCL/Perl/Python is preferred.
Education
- Bachelor's or Master's degree in Electronics / Electrical Engineering / VLSI / Microelectronics or related field.
