STA Engineer
STA Engineer
hrdwyr- Posted 13 hours ago
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Job Description
Job Description:
- Responsible for chip level STA convergence from early stages to signoff.
- Participate in top level floor plan and clock planning.
- IP & SoC timing constraints definition for all modes including DFT
- Constraints quality check
- Multimode-multi corner timing analysis.
- Timing ECO generation.
- Block and SoC level timing convergence.
- Block and SoC level Synthesis.
- Block and SoC level equivalence check.
Experience Required:
- 5 to 8 years of experience in SOC level timing convergence
- Synthesis and equivalence check
- Strong timing concepts
- Working knowledge of low power design involving multiple power domains.
- Proficiency in scripting languages such as TCL, Perl, or Python for automation.
- Familiarity with industry-standard EDA tools for STA like Tempus and PrimeTime
- Exposure to complex design having multiple asynchronous clocks.
More Info
Job Type:
Industry:
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Employment Type:
Key Skills
Block and SoC level Synthesis
Block and SoC level equivalence check
Block and SoC level timing convergence
Timing ECO generation
About Company
Skills:
Static Timing Analysis (STA), PERL, Python, Tcl, Synthesis, Cadence
Skills:
Synopsys Design Constraints (SDC), Static Timing Analysis (STA), primetime, Fusion Compiler, ICC2, Mentor Graphics
Skills:
Clp, automation, Scripting, LINT, prelayout STA, low power aspects, postlayout STA, Synthesis, cdc, SDC generation, demotion, SDC development, LEC, RTL Netlist based static checks, Dft, Timing Constraints, Timing Closure, Verification, promotion, equivalence checking
Skills:
QRC, primetime, Tempus, STA and signoff tools
Skills:
Sta, Synopsys, Synopsis Primetime, RTL2GDS, physical design EDA tools, Cadence