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Position Summary
About Samsung Semiconductor India Research (SSIR)Role and Responsibilities
. Must have 4 - 8 years of experience in SRAM Layout in advanced CMOS process
. Should be able to perform SRAM Memory layout development and physical verification activities for complex designs as per provided specifications.
. Should have expertise in layout area and routing optimization, design rules, yield and reliability issues.
. Good understanding of layout fundamentals i.e. Electro-migration, Latch-up, coupling, crosstalk, IR-drop, parasitic analysis, matching, shielding, etc.
. Should have adequate knowledge of schematics, interface with circuit designer and CAD team.
. Understanding layout effects on the circuit such as speed, capacitance, power and area etc.,
Skills and Qualifications
Experience - 4 to 8 Years of experience
Qualifications
Disclaimer
Samsung Semiconductor India Research (SSIR), a division of Samsung R&D India - Bangalore Pvt. Ltdis dedicated to employing a diverse workforce and providing Equal Employment Opportunity to all individuals, regardless of their religion, gender, age, marital status, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.
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Samsung R&D Institute India-Bangalore (SRI-B) is the largest R&D Center outside of South Korea and a key innovation hub in the Samsung group.
Job ID: 147882821
Skills:
shielding , power optimization , Memory Layout design, Statistical analysis of circuits, SRAM layouts, LVS, Custom Mixed-signal layouts, Dfm, EMIR, track planning, Basic concepts of matching, DRC, fabrication steps and flow, Reliability Analysis, analog mixed-signal design concepts, Circuit Design, Layout Design
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