The development of product grade SRAM memory IP s covering the following phases:
Layout Design of SRAM Memory IPs
Layout checks like LVS,DRC,DFM, EMIR
Review of Layouts and extend help for other Layout teams
Design Kit prep from layout side, verification and validation
Layout automation and script support
Being a good team-player taking key initiatives for productivity improvements and innovation
Sign off and release into dedicated IP validation test chips
Specification and documentation
Support of the silicon bring up and characterization

Required Qualifications :

Bachelor s degree with 8+ years or master s degree with 6+ years experience in semiconductors / Microelectronics / VLSI engineering.
Practical experiences in Memory and Custom Mixed-signal layouts at one or several of the following areas:
Memory Layout design and NVM architecture & concepts
Experience in NVM memory layout, SRAM layouts and Testchip integration will be an added advantage
Hands on knowledge of state-of-the-art memory or analog layout flows
Familiarity with Custom digital layout (i.e high speed logic paths)
Proficient in Basic concepts of matching, shielding, power optimization and track planning
Proficient in handling EDA tools from Synopsis, Mentor and Cadence used for layout design like schematic/layout editor, parasitic extraction tools, DRC, LVS, DFM, EMIR, etc.
Knowledge of layout effects (like matching, proximity effects etc)
Basic understanding of fabrication steps and flow.
General analog mixed-signal design concepts
Circuit design, Reliability analysis, Statistical analysis of circuits
Good understanding of CDL netlist and circuit hierarchy definition
Tiler / compiler concepts, design layout compatible for tiler approach and verify
Top level power routing and metal stack arrangement

Preferred Qualifications:

In depth familiarity with layout of analog and mixed signal CMOS circuits
Programming experience applicable to design flow automation tasks
The capability to work within a very dynamic interdisciplinary environment
as well as dedicated knowledge of 45/32/28/14nm and below technology nodes are an advantage.
You are flexible, highly motivated and have a team-oriented working style.
You have shown the ability to communicate as well as work efficiently in an international
multi-disciplinary environment.
Strong debugging, analytical and trouble shooting skills
Strong written and verbal communication skills in English are a must.

Memory Layout Engineer (SRAM/NVM)