Sr. Systems Design Engineer

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SENIOR SYSTEMS DESIGN ENGINEER

About The Position

The AMD CGC High-Speed IO Engineering Team is on the lookout for a dynamic, energetic High-Speed IO System Test Engineer to join our growing team in Bangalore. As a key contributor to the success of AMD's product portfolio, you will be part of a high-performance AMD team driving the delivery of high quality, industry leading product technology to market. The High-Speed IO Engineering team fosters and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. You will be working with the rest of the Global IO Teams to implement processes and best in class processes in the India Team.

The Person

Ideal candidate would be the one who is an expert at validation/characterization/Electrical and Link/protocol layer Compliance of High-Speed IOs, test architecture and test plan development, clear communication, and presentation skills along with diligent documentation of work. The High-Speed IO IP System Test Engineer will also be providing test reports to the AMD customer of the corresponding SOC products. You will be working with Industry leading companies and individuals in defining new specification for some of the newest technology in the industry. Passion to go beyond the call of duty and innovate for higher efficiency would be a key differentiator.

Key Responsibilities:

• Defining and executing overall High-Speed IO Electrical ,functional, Link/protocol Layer test plans(CTS) and validation strategy for AMD Semi-Custom SOC products including the compliance and logo testing related to the various High-Speed IOs such as MIPI MPHY UFS Gear 5/4/3, PCIe Gen4/3, USB4/USB3 Gen2/Gen1, HDMI, DP, DPoC etc. using hardware & software validation tools, oscilloscopes, BERT, Protocol & logic analyzers.
• Working closely with supporting teams in SOC design, High-Speed IO IP development, Board Design, Simulation, firmware and diagnostics ensuring readiness for first silicon arrival, electrical characterization across PVT, Link and Protocol layer compliance, submitting the test reports to different stake holders and blessing the IO.
• Participate and contribute to help in RCA of various High-Speed IO related issues throughout the development life cycle.
• Participate in enhancing AMD's High-Speed IO validation capabilities, including tool and script development, technical and procedural methodology enhancement, and various internal and cross-functional technical initiatives.
• Engaging with the various High-Speed IO suppliers in support of the SOC system development and the validation execution.

Preferred Experience:

• 5-10 years of IO Electrical and Logo, Protocol and Link layer Compliance Experience in at least one or several of Latest cutting Edge HSIOs such as UFS MIPI MPHY Gear 5/4/3, PCIe Gen6/5/4, USB4/3 etc.
• Working knowledge of any one or multiple High Speed IO technologies such as USB, HDMI, DP, DPoC, PCIe and others (SVI, I2C, JTAG etc.) that fall into a category we call MiscIO. Having a strong background in SI work with High-Speed IO technologies is a major plus.
• Solid understanding and vast experience on Test and characterization methodology of DDR or High-Speed IO interfaces which includes electrical compliance specifications such as eye diagram, differential signaling, jitter decomposition and analysis, Receiver-Jitter-Tolerance, transmission line considerations, Embedding/de-embedding, Measuring Various Types of channel losses, S-param measurements and Analysis, Phase Noise and Spectrum analysis, Spur measurements etc. through Latest HSIOs Lab Equipment.
• Experience in using High End oscilloscopes, J-BERT, Network analyzers ENA/VNA/TDR, spectrum analyzer, Phase Noise Analyzers, clock recovery, signal/function generators, Protocol, and logic analyzers etc.
• Exposure to Pre-silicon USB/UFS/PCIe Emulation, HSIOIs-ATE test methodologies, familiar with HSIOs Architecture-Enumeration, Data transfer, Packets, Interrupts, Wakeups, Bandwidth requirement and limitations, use cases, Functional debugs is a plus.
• Good to have Team Lead capabilities with proven track record of technical expertise in the development & execution of platform level electrical & functional/link layer Compliance/Logo test plans.
• Should be able to use PCB design tools such as Orcad, Allegro, Mentor Graphics etc.
• Having working knowledge of any one of SI Simulation tools such as Ansys HFSS, Power-SI, Sigrity, ADS is a major plus.
• Automation skills especially using Python or any other languages like C/C++, Perl, Ruby, C# is desirable.
• Must have excellent written and verbal communication skills for both internal and customer facing interaction.
• Attention to detail and the ability to analyze data quickly is a must.

Academic Credentials

• E/B.Tech/M.Tech in Electrical or Electronics Engineering with 5+ years of related experience

LOCATION: Bangalore, India

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Benefits offered are described: .

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants needs under the respective laws throughout all stages of the recruitment and selection process.

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This posting is for an existing vacancy.