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Key Responsibilities
Job ID: 148698143
Skills:
Perl, Python, Tcl, Chip Design, EDA Tools, RTL, ASIC Design, Product Marketing, Electronics Engineering, Physical Design, Digital Implementation, PPA Optimization
Skills:
routing, Perl, Python, Tcl, ASIC design flow, Synthesis, Timing Analysis, signoff, EDA Tools, Timing Closure, Placement, PPA optimization, RTL-to-GDSII
Skills:
Verilog, ASIC design flows, AI-driven chip design, LLM technologies, Hardware Verification, systemverilog
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