Perl, Python, Tcl, Chip Design, EDA Tools, RTL, ASIC Design, Product Marketing, Electronics Engineering, Physical Design, Digital Implementation, PPA Optimization

routing, Perl, Python, Tcl, ASIC design flow, Synthesis, Timing Analysis, signoff, EDA Tools, Timing Closure, Placement, PPA optimization, RTL-to-GDSII

Verilog, ASIC design flows, AI-driven chip design, LLM technologies, Hardware Verification, systemverilog