Sr Principal Design Engineer

Key Responsibilities

• Develop and maintain robust verification testbenches for complex RTL designs.
• Perform functional verification using Verilog and HVL languages (SystemVerilog, Specman e) with UVM/OVM/eRM methodologies.
• Define and implement constrained random verification environments and strategies.
• Develop assertions for design checking and contribute to formal verification closure.
• Drive functional and code coverage closure to ensure design completeness.
• Perform RTL and Gate-Level Simulation (GLS) with or without SDF annotation.
• Debug complex simulation failures across RTL, testbench, and GLS environments.
• Develop reusable verification components and improve testbench architecture.
• Automate verification flows using Perl and Tcl scripting.
• Manage project schedules, milestones, and delivery independently.
• Collaborate with design, architecture, and cross-functional teams for issue resolution.