Debugging, Test Planning, Simulation, systemverilog, Uvm, IP verification, Testbench development, Verification architecture, Mentoring

code coverage , closure , Ovm, Perl, Tcl Scripting, Verilog, SDF, automation, Specman, SV, assertions development, constraint randomization, RTL, Uvm, GLS, formal verification, eRM methodology, test-bench development, HVL

testbench development, UVM methodology, test plan reviews, debugging complex IP designs, systemverilog

arm architecture , Tcl, C, Perl, Pcie, Synopsys, Uvm, CXL, ARM verification tools, Mentor, Cadence