Debugging, Test architecture definition, Scan Insertion, Timing constraints for test mode timing closure, Scan and ATPG for different fault models, LEC checks, Zero delay and timing simulations, RTL changes for DFT, Post silicon bring up, DFT ownership, IEEE1687 iJTAG compliant ICL PDL for functional manufacturing tests, Boundary scan ACJTAG IEEE 1500 implementation and verification, Low power CLP checks