Debugging, Test architecture definition, Low power CLP checks, LEC checks, Zero delay and timing simulations, RTL changes for DFT, Boundary scan ACJTAG IEEE 1500 implementation and verification, DFT ownership, Scan and ATPG for different fault models, Timing constraints for test mode timing closure, Scan Insertion, Post silicon bring up, IEEE1687 iJTAG compliant ICL PDL for functional manufacturing tests