Hands-On UVM at user level, pseudo and constrained random techniques, assertion-based verification techniques with System Verilog.
Verification of analog interface is a value add along with ARM based subsystem, core sight, security subsystem verification exposure.
3rd party, industry-standard simulator productivity improvements and breakthrough innovations, integration into ADI DV solutions and creating differentiating solutions
Evaluate, utilize existing and develop new verification infrastructure frameworks, tools, and methodologies to enhance the verification process for efficiency and quality
Job Requirements:
BTech/MTech degree in Electrical/Electronics/VLSI with 3-6 years of experience from reputed institutes
Strong hands-on experience in Cadence/Synopsys simulation and debug tools like Xcelium/VCS, vManager, Verisium, Verdi or similar is required
Debugging of Gate Level Simulation (GLS), waiving Timing Violations approved by designer.
Coding up in C tests on M3 Series Cortex based products.
Expertise in automation and scripting languages like Perl, Python, and shell scripting
Proficient in Version control systems, such as Perforce, SVN, SOS
Proficient in Verilog, System Verilog and UVM
Ability to manage multiple tasks and work effectively in a fast-paced environment
