Job Description
Location: Bangalore, India
Experience: 6 to 8 Years
Company: Tessolve Semiconductor Pvt. Ltd.
About Tessolve
Tessolve is a leading provider of engineering solutions for silicon and system product companies, offering services in VLSI Design, Embedded Systems, Test Engineering, and PCB Design. With a strong foundation in semiconductor engineering and a global footprint, Tessolve is shaping the future of chip design and development.
Job Description
We are seeking a skilled Senior Verification Engineer to join our growing team in Bangalore. The ideal candidate will have a strong background in RTL verification, with hands-on experience in UVM methodology, and a track record of delivering high-quality verification solutions for complex SoCs and IPs.
Key Responsibilities
Develop and execute test plans for IP/Sub-System/SoC level verification.
Develop reusable verification components using SystemVerilog/UVM.
Write and maintain directed and constrained-random test cases.
Perform functional coverage analysis and close coverage gaps.
Work closely with design teams to debug and resolve issues.
Participate in verification reviews, code reviews, and documentation.
Mentor junior engineers and provide technical guidance.
Required Skills
6 to 8 years of experience in ASIC/SoC verification.
Strong expertise in SystemVerilog and UVM.
Experience in testbench architecture and development.
Solid understanding of verification methodologies and functional coverage.
Hands-on experience with simulation tools (VCS/Questa/Incisive).
Good debugging and problem-solving skills.
Experience with scripting languages like Python, Perl, or TCL is a plus.
Knowledge of protocols like AMBA (AXI/AHB/APB), PCIe, USB, or DDR is desirable.
Preferred Qualifications
Bachelor's or Master's degree in Electronics, Electrical, or Computer Engineering.
Exposure to formal verification is a plus.
Strong communication and teamwork skills.
