Job Summary
We are looking for a seasoned STA Engineer with 7+ years of experience in Static Timing Analysis for complex SoC designs. The ideal candidate will have hands-on expertise in timing closure, sign-off methodologies, and cross-functional collaboration with design, physical design, and verification teams.
Key Responsibilities
- Perform Static Timing Analysis (STA) and timing sign-off at block and full-chip level.
- Work closely with RTL, synthesis, and physical design teams to ensure timing convergence.
- Analyze timing reports and debug violations (setup, hold, transition, etc.).
- Develop timing constraints (SDC) for pre- and post-layout stages.
- Conduct timing ECOs for both functional and test modes.
- Drive timing closure across multiple PVT corners and modes.
- Perform clock analysis, skew analysis, and optimize clock paths.
- Support tape-out and interface with foundry for timing sign-off requirements.
Required Skills & Experience
- Strong hands-on experience with STA tools like PrimeTime, Tempus, or equivalent.
- In-depth knowledge of SDC constraints, timing checks, and ECO methodologies.
- Good understanding of synthesis and physical design flows.
- Familiarity with multi-mode multi-corner (MMMC) analysis.
- Solid scripting skills in Tcl, Perl, Python or Shell for automation.
- Experience working on complex SoC or ASIC projects at advanced technology nodes (e.g., 7nm/5nm/16nm).
- Excellent debugging and problem-solving skills.
- Ability to work independently and lead timing closure tasks with minimal supervision.
Good to Have
- Exposure to low power design techniques and UPF flow.
- Familiarity with timing library characterization and variation analysis.
- Knowledge of signal integrity, cross-talk, and OCV handling.
Qualifications
- B.E./B.Tech or M.E./M.Tech in Electronics/Electrical/Computer Engineering or related field.
