As a Senior CAD Engineer within Analog Devices Engineering Enablement organization, you'll play a pivotal role in ensuring the quality and reliability of our semiconductor designs. You'll be instrumental in developing and testing the Quality Assurance (QA) framework used for validating Process Design Kits (PDKs), which are crucial for the design and manufacturing of our cutting-edge analog, mixed-signal, power management, and DSP products.
In this individual contributor role, you'll leverage your programming skills and circuit design expertise to develop, support, enhance, and test the PDK QA flow at ADI. Your work will directly impact the quality of PDK deliverables, including schematic symbols, layout p-cells, CDFs, DRC/LVS decks, parasitic extraction technology files, ESD verification, and other reliability-based flows. You'll also contribute to the development of PDKs for both internal and external process technologies, utilizing industry-leading CAD software such as Cadence, Mentor, and Keysight, alongside our internally developed tools.
Primary Responsibilities:
- Develop device-level layout generators (PCELLs) to ensure accurate and efficient design.
- Create robust physical verification (DRC/LVS) rules and parasitic extraction flows for comprehensive design validation.
- Collaborate closely with PDK component developers to create and enhance test cases, actively improving QA coverage.
- Interpret process, assembly, and packaging design rule specifications to ensure test cases accurately reflect implemented DRC checks.
- Understand Layout vs. Schematic (LVS) flow intent and develop representative test cases for validating LVS decks.
- Drive automatic test case generation and unit testing to ensure adequate test coverage for all PDK components.
- Perform thorough test case debugging, investigating PASS/FAIL scenarios to ensure functionality meets requirements.
- Provide expert technical CAD support to the ADI design community.
- Work closely with design teams to understand their requirements and collaborate with device modeling, process development, and foundry groups to optimize CAD tool and methodology usage.
- Create comprehensive test cases for validating netlists generated for internal and external analog circuit simulation tools.
- Generate test cases to verify the accuracy of Parasitic Resistance/Capacitance extraction technology files.
- Validate tech files used in ESD verification, including topology checks, ESD resistance, and current density checks.
- Collaborate with EDA software vendors to resolve tool bugs and drive the implementation of new features.
Qualifications:
- Minimum of 6 years of experience in developing PDKs and programming for automation.
- BS/MS in Electrical or Computer Engineering with a strong emphasis on IC design and semiconductor processes.
- Essential knowledge of Python Programming Language and Cadence Skill Language.
- Proven proficiency in other programming languages such as Perl, Tcl, and Bash.
- Demonstrated experience undertaking automation projects.
- Strong understanding of analog/mixed-signal simulation tools.
- Familiarity with physical verification (DRC/LVS) tools.
- Knowledge of parasitic extraction tools.
- Familiarity with revision control systems and collaboration tools is a plus.
- Must possess excellent verbal and written communication skills.
- Must be detail-oriented, well-organized, and a versatile team player.
