Soc Verification Lead
Soc Verification Lead
silicon patterns- Posted 3 months ago
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Job Description
Job Title: SoC Verification Lead Engineer
Experience: 6+ Years
Location: Bangalore
Role Overview
:We are looking for an experienced SoC Verification Lead to drive end-to-end verification of complex SoCs. The candidate will be responsible for leading verification efforts, mentoring teams, and ensuring high-quality silicon delivery
.Key Responsibilities
- :Lead SoC verification activities including planning, execution, and closur
- eDefine verification strategy, test plans, and methodologie
- sDevelop and review testbenches using SystemVerilog/UV
- MHandle integration-level verification for multiple IPs (e.g., PCIe, DDR, Ethernet, etc.
- )Drive coverage closure (functional, code, assertion
- )Debug complex SoC-level issues and coordinate with design team
- sLead and mentor a team of verification engineer
- sEnsure timely delivery with high-quality standard
sRequired Skills
- :Strong expertise in SystemVerilog and UVM methodolog
- yExperience in SoC/Subsystem level verificatio
- nHands-on experience with high-speed protocols (PCIe/DDR/Ethernet/AXI
- )Strong debugging and problem-solving skill
- sExperience with simulation, emulation is a plu
- sKnowledge of scripting languages (Python/Perl/Shell)
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About Company
Skills:
Vcs, DDR, Pcie, Usb, Ethernet, AHB, CHI, Xcelium, Uvm, UPF, coverage-driven verification, VIP integration and customization, LPDDR, low-power verification, Ace, Emulation, debug using industry-standard simulators, FPGA prototyping, systemverilog, constrained random methodology, Axi, AMBA, APB, Questa, CXL, CPF, IP and SoC level verification, high-speed protocols, SVA
Skills:
shell scripting, Perl, Python, Tcl, mixed-signal design verification, Cadence Spectre simulation, Cadence Mixed-Signal Design Environment, SV UVM-based testbenches, VerilogAMS, behavioral modeling, systemverilog
Skills:
Usb, Vcs, DDR, Perl, Pcie, Ethernet, Python, Tcl, Verdi, Uvm, systemverilog, CXL, LPDDR, high-speed protocols
Skills:
Test Case Creation, Shell, Perl, Python, Advanced Debugging skills, Uvm, testbench development, coverage-driven verification, Computer Architecture concepts, Formal Verification techniques, Functional Verification, Rtl Design