Vcs, DDR, Pcie, Usb, Ethernet, AHB, CHI, Xcelium, Uvm, UPF, coverage-driven verification, VIP integration and customization, LPDDR, low-power verification, Ace, Emulation, debug using industry-standard simulators, FPGA prototyping, systemverilog, constrained random methodology, Axi, AMBA, APB, Questa, CXL, CPF, IP and SoC level verification, high-speed protocols, SVA

shell scripting, Perl, Python, Tcl, mixed-signal design verification, Cadence Spectre simulation, Cadence Mixed-Signal Design Environment, SV UVM-based testbenches, VerilogAMS, behavioral modeling, systemverilog

Usb, Vcs, DDR, Perl, Pcie, Ethernet, Python, Tcl, Verdi, Uvm, systemverilog, CXL, LPDDR, high-speed protocols

Test Case Creation, Shell, Perl, Python, Advanced Debugging skills, Uvm, testbench development, coverage-driven verification, Computer Architecture concepts, Formal Verification techniques, Functional Verification, Rtl Design