SoC Frontend Design Engineer

We are seeking a skilled SoC Frontend Design Engineer to join our integrated circuit (IC) design team. Will be focusing on RTL design, digital logic design, synthesis, linting, timing analysis, and verification for ASIC projects. Work closely with cross-functional teams to deliver high-quality and efficient SoC (System on Chip) designs. This role requires good knowledge of VHDL/Verilog, verification methodologies, testbench development, and debugging.

You have:

• Bachelor s Degree in Electrical, Computer Engineering, or a related field (Master s preferred)
• 3+ years of experience in RTL design and digital logic design. Proficiency in VHDL/Verilog for RTL design.
• Strong knowledge of digital logic design, synthesis, and timing analysis.
• Experience with linting tools and methodologies
• Familiarity with verification methodologies (UVM, System Verilog), testbench development, simulation, and functional coverage.
• Strong debugging skills to identify and resolve design issues
• Required Tools: Synopsys Design Compiler or Cadence Genus, Mentor Graphics QuestaSim, Spyglass VC

It would be nice if you also had:

• Familiarity with high-level synthesis (HLS) tools
• Knowledge of scripting languages such as Python, Tcl, or Perl for automation
• Develop RTL designs using VHDL/Verilog for ASIC projects
• Perform digital logic design, synthesis, and timing analysis
• Conduct linting and static analysis to ensure code quality
• Develop and implement verification methodologies (UVM, System Verilog)
• Create and maintain testbenches for simulation and functional coverage
• Perform simulations and debugging to ensure design correctness
• Participate in design reviews and provide feedback to improve design quality