Role Overview
We are looking for an experienced
SoC Design Verification Engineer with strong expertise in
SystemVerilog and UVM for SoC-level integration verification, preferably on
ARM-based platforms. The candidate will be responsible for building and executing robust verification environments and ensuring high-quality RTL validation across complex SoCs.
Key Responsibilities
- Perform SoC-level integration verification, preferably for ARM-based SoCs (Cortex-M0+, Cortex-M4, etc.)
- Develop and maintain UVM-based verification environments
- Implement testbenches, test cases, and verification strategies using SystemVerilog, UVM, C/C++/Assembly
- Integrate and configure Verification IPs (VIPs) in SoC-level environments
- Verify hardware/software interactions, including DMA controllers and interrupt subsystems
- Perform Power Domain / Voltage Domain verification
- Execute power-aware simulations using CPF/UPF
- Develop and analyze code coverage, functional coverage, and SVA assertions
- Debug complex RTL and system-level issues
- Collaborate closely with RTL design, architecture, and firmware teams
Required Skills & Experience- Strong hands-on experience in SystemVerilog and UVM
- Experience in SoC-level integration verification
- Solid coding skills in SV/UVM/C/C++/Assembly
- Strong debugging and root-cause analysis skills
- Good understanding of ARM-based SoC architecture
- Experience with AMBA protocols (AHB/APB/AXI)
- Familiarity with peripherals such as:
- Understanding of memory subsystems:
- Knowledge of JTAG/SWD
- Good understanding of ARM CPU internals and ARM debug infrastructure
Preferred Qualifications
- Experience in coverage-driven verification methodologies
- Prior experience working on complex SoC platforms
- Exposure to low-power verification flows
Skills: soc-level integration verification,verification ips,arm,silicon,soc,verification engineer,arm platform,uvm-based environments,firmware-driven validation,integration and system verification
