THE ROLE:
As a member of the EPIC server soc team , you will help bring to life cutting-edge designs. As a member of the Physcial design/soc integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success.
THE PERSON:
A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills.
KEY RESPONSIBILITIES:
- Working on Constraints, Full chip netlist generation, static timing analysis setup and signoff of multi-corner multi-voltage designs.
- Owning timing execution to meet timing requirements including timing budgeting, repeater planning, constraints/exceptions generation and management
- Areas of focus include Constraints generation, verification, Timing analysis and verification, extraction and noise glitch analysis
- Engaging closely with Design teams to understand the design, constraints and convergence challenges and providing ECOs with a focus on PPA and TAT optimizations.
- Hierarchical timing analysis and convergence at block, section and fullchip level.
PREFERRED EXPERIENCE:
- 10+ years of professional experience in Constraints generation, Synthesis, STA, full chip timing and physical design, preferably with high performance designs.
- Demonstrated ability in areas of Timing analysis, timing convergence, SI/Noise analysis, Signoff quality (PVT, process variation effects, guardbanding, etc), Timing ECOs, PV/Noise modelling, .libs, is a must.
- Multi-voltage scenarios design handling knowledge is expected. STA closure/convergence execution on Low power designs is an added advantage.
- Expertise in industry standard EDA tools (Primetime) and ASIC design flow is required.
- Hands-on experience with Physical Design implementation is a plus
- Proficiency in scripting language, such as, Perl and Tcl.
- Versatility with scripts to automate design flow, analysis
- Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams
- Experience in 16/14/10/7/5nm nodes
- Good understanding of computer organization/architecture is preferred.
- Strong analytical/problem solving skills and pronounced attention to details.
ACADEMIC CREDENTIALS:
- Bachelors or Masters degree in computer engineering/Electrical/Electonics and communication Engineering
