Engineer with a good attitude, strong analytical skills, effective communication, and excellent problem-solving abilities.
KEY RESPONSIBILITIES:
- Own critical CPU units and drive to convergence from RTL-to-GDSII - synthesis, floor-planning, place and route, timing closure, and signoff
- Understand the micro-architecture to perform feasibility studies on performance, power, and area (PPA) tradeoffs for design closure.
- Develop and improve physical design methodologies and customize recipes across various implementation steps to optimize PPA.
- Implement floor plan, synthesis, placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), EM/IR and signoff.
- Handling different PNR tools - Synopsys fusion compiler, Cadence, PrimeTime, StarRC, Calibre, Apache Redhawk
PREFERRED EXPERIENCE:
- 12+ years of professional experience in physical design, preferably with high-performance designs.
- Must have closed high-performance IPs- CPU/GPU/DPU/memory controller, etc
- Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality; familiarity with tools for schematics, layout, and circuit/logic simulation
- Versatility with scripts to automate design flow - Perl/Tcl/Python
- Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams
- Experience in advanced sub 7nm nodes
- Excellent physical design and timing background.
- A good understanding of computer architecture is preferred.
- Strong analytical/problem-solving skills and pronounced attention to detail.
ACADEMIC CREDENTIALS:
- Qualification: Bachelors or Masters in Electronics/Electrical Engineering
