Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 8 years of experience in bringing-up and validating at least one high-speed serial or parallel interface (e.g., PCIe, UCIe, DDR, HBM, Ethernet, etc.).
- 8 years of experience in analyzing board schematics and working with scopes, logic analyzers, protocol analyzers, BERT, etc
- 3 years of experience leading a post-silicon validation team with ownership on electrical validation of one or more high speed interfaces.
- Experience of co-working with firmware/software teams to debug issues.
- Experience in people management, developing employees.
Preferred qualifications:
- Experience in bringing up multiple serial and parallel high speed interfaces.
- Experience in programming/scripting in C, C++, Python, Perl or TCL.
- Experience in using emulation or prototyping platforms.
- Experience in end-to-end post-silicon validation of an SoC (bring-up, features validation, electrical, power and performance characterization, etc.).
- Understanding of SoC architecture and interfaces (e.g., AXI, DDR, PCIe, etc.).
About The Job
In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
The Platform Enablement team is responsible for the development, bring-up and qualification, deployment, sustaining the quality of our AI/ML custom silicon. We plan and integrate hardware and software stacks and operate them on emulation, simulation and post-silicon platforms. We work closely with silicon design, platform hardware, firmware and software teams to enable on-time delivery of high quality silicon products.
In this role, you will be working on building, managing and leading a team of engineers responsible for post-silicon validation of AI/ML SoC which uses technology, working closely with the architecture, design, verification, firmware, software and platform leads, ensure timely silicon bring-up, enablement and debug closures and driving the preparation of necessary tests and collaterals for effective silicon bring-up, validation and debug, working with various IP vendors ensuring sufficient pre-sival
and enablement is done on vendor deliverables.
As a manager, you will be responsible for growing the team through hiring, developing a psychologically safe environment for the team to succeed, enabling people development through effective career conversations, mentoring and building a strong community.The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving team behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
Responsibilities
- Build, manage and lead the team responsible for post silicon validation of Artificial Intelligence/Machine Learning (AI/ML) System on a Chip (SoCs).
- Lead and enable the team to power-on Tensor Processing Unit (TPU) SoC silicon and bring it up through reset, boot and bare metal content or Operating System (OS).
- Drive the enablement of all key high-speed serial and parallel interfaces in TPU silicon.
- Collaborate with architecture, design and verification teams to propose, implement and enable DFV (Design for Validation) and DFD (Design for Debug) features on silicon and develop and review post silicon test plans, coverage and debug.
- Drive all the people management functions including, but not limited to, hiring, people development, prioritizing and managing resources to achieve project execution timelines.
Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .
