Silicon RTL IP/Subsystem Senior Engineer, Google Cloud

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 5 years of experience in Application-specific integrated circuit (ASIC) development with Verilog/SystemVerilog, VHDL, or Chisel.
• Experience in ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT).
• Experience in micro-architecture and designing IPs and subsystems.

Preferred qualifications:

• Experience with coding languages (e.g., Python or Perl).
• Experience in System on a Chip (SoC) designs and integration flows.
• Knowledge of arithmetic units, bus architectures, processor design, accelerators, or memory hierarchies.
• Knowledge of high performance and low power design techniques.

Responsibilities:

• Own microarchitecture and implementation of Internet Protocol (IPs) and subsystems.
• Work with Architecture, Firmware, and Software teams to drive feature closure and develop microarchitecture specifications.
• Drive design methodology, libraries, debug, and code review in coordination with other Internet Protocol (IPs) Design Verification (DV) teams and physical design teams.
• Identify and drive power, performance, and area improvements.