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Senior Verification Engineer will be responsible for identifying, analyzing, and resolving complex issues while working closely with cross-functional teams. You will contribute to improving overall product quality by developing and implementing test strategies, ensuring seamless integration and system performance. Enhance automation processes and work on advanced networking technologies. Drive efficiency, optimize workflows, and adopt industry best practices to improve system.
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Job ID: 106987651
Skills:
Python, Systemc, MDV, simulation scripts, hybrid testbenches, regression systems, verification execution, Uvm, systemverilog, testbenches, CDV, coverage models
Skills:
Vcs, JIRA, Git, Bitbucket, Perl, Verilog, Python, Tcl, CVS, Gate-Level Simulation, Xcelium, Palladium, Uvm, systemverilog, Assertions, Zebu, Protium, Questa, RTL-to-Gate-Level Simulation, HAPS, SoC Verification
Skills:
Fpga, Perl, Python, RTL, Uvm, systemverilog, AMBA bus protocols, Baremetal processor environments, low power verification methods, object-oriented design, formal verification methods, transaction level modeling, test plan development, emulation platforms
Skills:
Usb, Jtag, Perl, Pcie, Ethernet, System Verilog, Python, UVM methodology, Design for Debug, scripting in Linux Unix environments, SoC architecture verification, TSN, ARM based SoC verification, High speed USB
Skills:
Vcs, DDR, Shell, Pcie, Perl, Ethernet, Python, Verdi, CHI, IUS, Uvm, systemverilog, Axi, Questa, AHB
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