Python, Systemc, MDV, simulation scripts, hybrid testbenches, regression systems, verification execution, Uvm, systemverilog, testbenches, CDV, coverage models

Vcs, JIRA, Git, Bitbucket, Perl, Verilog, Python, Tcl, CVS, Gate-Level Simulation, Xcelium, Palladium, Uvm, systemverilog, Assertions, Zebu, Protium, Questa, RTL-to-Gate-Level Simulation, HAPS, SoC Verification

Fpga, Perl, Python, RTL, Uvm, systemverilog, AMBA bus protocols, Baremetal processor environments, low power verification methods, object-oriented design, formal verification methods, transaction level modeling, test plan development, emulation platforms

Vcs, DDR, Shell, Pcie, Perl, Ethernet, Python, Verdi, CHI, IUS, Uvm, systemverilog, Axi, Questa, AHB

Usb, Jtag, Perl, Pcie, Ethernet, System Verilog, Python, UVM methodology, Design for Debug, scripting in Linux Unix environments, SoC architecture verification, TSN, ARM based SoC verification, High speed USB

Git, Perl, Jira, Python, Uvm, systemverilog

scoreboard , Perl, Scripting Languages, Python, Uvm, Agents, constrained random techniques, sequencers, HVLs, testbenches, Gate simulations, debugging RTL, monitors

Git, Shell scripting, Python, WLAN standards IEEE 802.11

Verilog, Unix, Python, Perl, Shell, Linux, systemverilog, Uvm

arinc 429 , C, Doors, Defect Tracking, Spi, JIRA, Svn, Jama, Clearcase, I2c, VxWorks, Python, Rtrt, Uart, Can, Git, Linux, DO-160, configuration management tools, Polarion, SIL testing, Communication Protocols, PikeOS, MIL-STD-1553, DO-254, RTOS environments, DO-178C, requirements management tools