Senior Verification Engineer, DDR PHY
Senior Verification Engineer, DDR PHY
Randstad Sourceright- Posted 8 hours ago
- Be among the first 10 applicants
Job Description
Position: Senior Verification Engineer, DDR PHY (IRT60ST RM 4494)
Verification ownership from testplan to vector delivery, regression debug, and quality sign-off for DDR PHY.
Must-have
Verification ownership from testplan to vector delivery, regression debug, and quality sign-off for DDR PHY.
Must-have
- DDR PHY architecture, DFI protocol, JEDEC standards (latest gens)
- LPDDR5/LPDDR4 hands-on experience
- Verilog/SystemVerilog, UVM/OVM
- Strong debug and root-cause skills, including SS/SoC/post-silicon issues
- Perl scripting
- Post-silicon bring-up, HW-SW debug
- AHB/AXI protocol knowledge
More Info
Key Skills
Post-silicon bring-up HW-SW debug
AXI protocol
DDR PHY architecture
JEDEC standards
DFI protocol
LPDDR4
debug and root-cause skills
SS SoC post-silicon issues
LPDDR5
About Company
Skills:
PCIE protocol - Gen3 and above, Usb, Verilog, Sata, Python, Perl, Uvm, CXL-based designs, PCI Express, systemverilog, Industry standard verification tools for simulation and debug, Functional coverage based constrained random verification, VMM, DV methodologies
Skills:
C, Perl, Verilog, Xml, Python, Tcl, VHDL, Uvm, systemverilog