PCIE protocol - Gen3 and above, Usb, Verilog, Sata, Python, Perl, Uvm, CXL-based designs, PCI Express, systemverilog, Industry standard verification tools for simulation and debug, Functional coverage based constrained random verification, VMM, DV methodologies

C, Perl, Verilog, Xml, Python, Tcl, VHDL, Uvm, systemverilog