Senior Test Engineer (ATE – NI STS / Advantest V93K)

• Location: India (Bangalore / Coimbatore – flexible based on project)
• Work Mode: On-site
• Experience Range: 3–5 Years
• Role Overview
  
  

We are looking for a Senior Test Engineer with hands-on experience in ATE platforms (NI STS / Advantest V93K) to support silicon validation and production test development. The role involves end-to-end test program development, characterization, and debugging across wafer sort and final test stages. The candidate will work closely with Product Engineering, Foundry, and Reliability teams during NPI and volume phases.

• Key Responsibilities
• Develop ATE test programs from scratch for wafer sort and final test environments
• Integrate multiple test functions into optimized test flows for NPI silicon bring-up
• Drive end-to-end test engineering activities with Product, Test, Reliability, and Foundry teams
• Develop and debug test interface hardware schematics
• Analyze wafer sort (WS) and final test (FT) data to define screening specifications
• Develop, debug, and optimize test patterns and test flows
• Perform silicon characterization and debug for new designs and process nodes
• Support product reliability studies including HTOL testing
• Evaluate performance and power characteristics over product lifecycle
• Identify yield issues and support yield improvement activities
• Collaborate across cross-functional teams for issue resolution and product qualification
• Document test methodologies, characterization reports, and debug findings
• Required Qualifications
• Bachelor's or Master's degree in Electronics, Electrical Engineering, or related field
• 3–5 years of experience in semiconductor test engineering (ATE environment)
• Experience in wafer sort and final test for semiconductor devices
• Technical Skills
  
  

ATE Platforms

• NI STS (Semiconductor Test System)
• Advantest V93K
  
  

Programming & Scripting

• C / C++
  
  

Device & Domain Expertise

• Memory (Digital / Analog)
• Mixed-Signal Devices
• Power Management ICs
  
  

Test & Validation

• Wafer Sort (WS) and Final Test (FT)
• Silicon Characterization & Debug
• Test Flow Development & Optimization
  
  

Hardware & Debug

• Test Interface Hardware (TIH) schematic understanding
• Debug of test hardware and test setups