Senior Staff IP Verification Engineer

• Specify, design, and implement state-of-the-art verification environments for the DesignWare family of synthesizable cores.
• Perform verification tasks for IP cores, working closely with RTL designers.
• Drive ownership of critical areas of verification along with a team of talented verification engineers.
• Develop and implement advanced test plans and test environments at both unit and system levels.
• Code and debug test cases, implementing complex checkers and assertions.
• Extract and review functional coverage (FC) and code coverage metrics, ensuring quality metric goals are met.
• Manage regressions and contribute to the continuous improvement of verification strategies and test environments.

The Impact You Will Have:

• Enhance the quality and efficiency of our verification processes, ensuring robust and reliable IP cores.
• Contribute to the development of cutting-edge technologies that power the Era of Smart Everything.
• Enable the creation of high-performance silicon chips and software content, driving innovation in various industries.
• Collaborate with a global team of experienced verification engineers, fostering a culture of knowledge sharing and continuous learning.
• Play a key role in the success of Synopsys DesignWare IP Verification R&D team, contributing to our leadership in chip design and software security.

What You'll Need:

• BS/MS in Electrical Engineering or Electronics and Communication Engineering with 8+ years of relevant experience.
• Proven experience in developing HVL (System Verilog/UVM) based test environments.
• Expertise in developing and implementing test plans, checkers, and assertions.
• Proficiency in extracting verification metrics such as functional coverage and code coverage.
• Experience with memory interface protocols (DDR, LPDDR) and IP design and verification processes.