Senior Staff Engineer

Senior Staff Engineer – Physical Design (Full-Chip STA)

Location: Bengaluru, India

Experience: 10–16 Years

Role

Own Full-Chip STA Signoff for next-generation high-performance SoCs. Lead timing architecture, signoff methodology, and timing convergence across advanced technology nodes, enabling first-pass silicon success.

What You'll Do

• Own end-to-end Full-Chip Static Timing Analysis (STA) from RTL through tapeout.
• Drive timing signoff across MMMC scenarios, ensuring closure of setup, hold, SI, Crosstalk, OCV/AOCV/POCV, CRPR, and timing exceptions.
• Define and implement timing constraints (SDC), timing budgets, hierarchical timing methodologies, and signoff strategies.
• Lead timing convergence through ECO implementation, path optimization, and cross-functional closure with RTL, Synthesis, CTS, Physical Design, DFT, and Architecture teams.
• Drive signoff for multi-voltage, low-power (UPF/CPF), CDC/RDC, and advanced-node designs.
• Develop scalable STA automation and methodologies using Tcl/Python/Perl to improve productivity and QoR.
• Mentor engineers, drive technical reviews, and establish timing signoff best practices across programs.

What You Bring

• 10–16 years of hands-on experience in Full-Chip STA for complex ASIC/SoC designs.
• Expert knowledge of PrimeTime, Cadence Tempus, and signoff methodologies.
• Deep expertise in MMMC, SI, Crosstalk, OCV/AOCV/POCV, LVF, CRPR, SDC, ECO, Timing Constraints, Clock Architecture, CTS, and timing closure.
• Strong understanding of RTL, Synthesis, Physical Design, Floorplanning, CTS, Routing, and interaction with timing signoff.
• Experience with advanced technology nodes (7nm/5nm/3nm and below) and large multi-million gate SoCs.
• Hands-on experience in EM/IR awareness, Physical Signoff, and Power Integrity considerations impacting timing.
• Strong scripting skills in Tcl; Python/Perl is an added advantage.

Preferred

• Experience with CPU, GPU, AI/ML, Networking, Mobile, Storage, or Automotive SoCs.
• Exposure to Fusion Compiler, ICC2, Innovus, RedHawk/Voltus, and Formality.
• Experience leading multiple tapeouts and mentoring STA teams.

We're Looking For

A highly technical STA leader who can own full-chip timing signoff, architect scalable STA methodologies, solve the most challenging timing closure problems, and drive first-pass silicon success for next-generation semiconductor products.