power integrity , Shell, Perl, Python, Tcl, Physical Design signoff, Ansys RedHawk, IR EM analysis, Cadence Voltus

redhawk , Python, Routing, Perl, Tcl, OCV, Signoff, CTS, Fusion Compiler, advanced packaging technologies, ICC2, SDC development, Tempus, hierarchical STA, SI Crosstalk, StarRC, POCV, Placement, UPF Low-Power, floorplanning, CRPR, MCMM timing closure, AOCV, ECO timing closure

Wireshark, Zigbee, Wlan, Thread, Python, Iperf, Ellisys sniffers, Bluetooth BR, LE Audio

Perl, Verilog, Python, spyglass, VHDL, DDR memory controllers, PCIe protocols

Tensorflow, Pytorch, MLops, Terraform, Docker, Kubernetes, Python, AWS, LangChain, Scikit-learn, event-driven systems, Go, LangGraph

Logic Design, Tcl, Python, Perl, Mentor, MBIST OCC validation flows, Synopsys, Digital Circuit Design, Scan insertion and ATPG tools, Hierarchical DFT and SDC constraint management, SpyGlass DFT rules, Sta, Cadence, Physical design flows, SSN design and IEEE 1687 IJTAG standards, RTL design synthesis