Senior Staff Engineer
Senior Staff Engineer
Infineon TechnologiesThis job is no longer accepting applications
Job Description
Functional safety Design Verification tools methodology with FMEDA, Generating Fault list & Fault Simulations, coverage analysis w.r.t to ISO26262 standard and ASIL levels.
Your role
Key responsibilities in your new role
Qualifications And Skills To Help You Succeed
As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.
Are you in
We are on a journey to create the best Infineon for everyone.
We strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity.
Our hiring decisions are based on skills and experience. Even if you don't meet every requirement, we encourage you to apply.
Please let your recruiter know if you need any accommodations during the interview process.
Learn more about our various contact channels and about Diversity & Inclusion at Infineon.
Vidhi Thakkar
Your role
Key responsibilities in your new role
- Experience with FuSa - Functional safety Design Verification tools methodology with FMEDA, Generating Fault list & Fault Simulations, coverage analysis with respect to ISO26262 standard and ASIL levels.
- Working experience with Analog-on-top designs, Mixed signal DV experience in POL (Point of Load), Power stage, Gate drivers or Multi Phase controllers chips.
- Experience with AI- driven automation for verification workflow, debug acceleration, and automated test plan creation using JAMA.
- Should have developed multiple verification environments for complex IPs and SoCs by defining new test bench architecture, test plan, and using state-of-the-art methodologies such as metric-driven.
- Having knowledge in SoC verification covering RTL, Power Aware and gate-level simulations is preferable.
- Exposure to deployment of automation methods and assertion-based formal verification methodologists preferable.
Qualifications And Skills To Help You Succeed
- Education: B.E./B.Tech/M.E./M.Tech in Electronics.
- Experience: MS with 8+ years / BS with 9+ years.
- Candidate should have strong background in digital verification to develop advanced testbenches using System Verilog and UVM.
- Collaborate with Design, Analog, AMS team for thorough verification coverage & closure.
As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.
Are you in
We are on a journey to create the best Infineon for everyone.
We strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity.
Our hiring decisions are based on skills and experience. Even if you don't meet every requirement, we encourage you to apply.
Please let your recruiter know if you need any accommodations during the interview process.
Learn more about our various contact channels and about Diversity & Inclusion at Infineon.
Vidhi Thakkar
More Info
Job Type:
Industry:
Function:
Employment Type:
Key Skills
gate-level simulations
automation methods
Fault Simulations
test bench architecture
FMEDA
Functional safety Design Verification tools methodology
Gate drivers
Multi Phase controllers
ISO26262 standard
verification workflow
ASIL levels
Analog-on-top designs
verification environments for complex IPs and SoCs
Mixed signal DV
debug acceleration
automated test plan creation using JAMA
About Company
Skills:
Clp, Perl, Python, Tcl, Scan Insertion, Hybrid-TK Compression, SoC DFT Architecture, ATPG DRC analysis, P1500 implementation, Memory BIST implementation, JTAG BSCAN, MBIST, LEC, Bridging Cell-aware iddq fault models, iJTAG, Stuck at TDF, Logic and DRC analysis, Test coverage debug, ZERO delay and SDF based scan, LPCT, JTAG simulations, power analysis methodologies, LBIST
Skills:
Arm, Python, RTL simulation, Debug, functional coverage closure, RISC-V, regression automation, x86 architecture, Uvm, SVA, systemverilog
Skills:
Shell, Perl, Scripting, Tcl, debug methodologies, automation using Python, Uvm, assertion-based verification, systemverilog, regression frameworks, coverage closure, formal verification, Functional Verification
Skills:
simulator , compiler , C, Verilog, Arm, Python, System Verilog, Embedded C Verification, Assembler, Floating point instructions implementation verification, RISC-V, Uvm, Logic Verification, processor toolchains, functional processor simulators
Skills:
Perl scripting, C, Verilog, Python, Axi, Uvm, AHB, systemverilog