Functional safety Design Verification tools methodology with FMEDA, Generating Fault list & Fault Simulations, coverage analysis w.r.t to ISO26262 standard and ASIL levels
Key responsibilities in your new role
- Experience with FuSa - Functional safety Design Verification tools methodology with FMEDA, Generating Fault list & Fault Simulations, coverage analysis with respect to ISO26262 standard and ASIL levels.
- Working experience with Analog-on-top designs, Mixed signal DV experience in POL (Point of Load), Power stage, Gate drivers or Multi Phase controllers chips.
- Experience with AI- driven automation for verification workflow, debug acceleration, and automated test plan creation using JAMA.
- Should have developed multiple verification environments for complex IPs and SoCs by defining new test bench architecture, test plan, and using state-of-the-art methodologies such as metric-driven.
- Having knowledge in SoC verification covering RTL, Power Aware and gate-level simulations is preferable.
- Exposure to deployment of automation methods and assertion-based formal verification methodologists preferable.
Qualifications And Skills To Help You Succeed
- Education: B.E./B.Tech/M.E./M.Tech in Electronics.
- Experience: MS with 8+ years / BS with 9+ years.
- Candidate should have strong background in digital verification to develop advanced testbenches using System Verilog and UVM.
- Collaborate with Design, Analog, AMS team for thorough verification coverage & closure.
Contact:
[Confidential Information]
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