C, Pcie, Ethernet, SV, CXL, Uvm, UCIe, systemverilog

arm architecture , Usb, DDR, Perl, Pcie, Test Plan, Scripting, Python, Shell Programming, Tcl, Arm core, GIC, SMMU, Dms, verification checks, Arm system IP, verification plan, debug methodology, SoC Verification

Usb, DDR, Shell, Pcie, Perl, Ethernet, Python, CHI, Ace, RISC-V, ARM CPU, Uvm, systemverilog, Axi, CXL, SVA

UNIX, Verilog, System Verilog, Debugging, Windows, Automated flows for generating RTL, Digital IP development

Mentor, Uvm, firmware interaction, Synopsys, AMs, systemverilog, Cadence, Siemens, Calibration and link training flows, Register models, industry VIPs, Avery, SERDES

Fpga, Logic Design, Verilog, Sta, Synthesis, Power product design, TCL scripts, Scan Insertion, Timing Analysis, design constraints, Uvm, ATPG generation, regression frameworks, formal verification, Timing Constraints, synthesis scripts, ABV, RTL Coding, micro-architecture, Functional Verification, System-Verilog, Digital Verification

Perl, Python, Formal Verification methodologies, Axi, APB, JasperGold, AMBA protocols, VC Formal, Uvm, AHB, systemverilog

Perl, Python, constraint-random testing, Power-aware verification, formal static verification techniques, coverage-driven verification methodologies, Uvm, systemverilog

Python, Perl, AHB, JasperGold, Uvm, formal verification, VC Formal, systemverilog, APB, Axi, AMBA protocols