Logic Design, Rtl Design, Debug skills, Synthesis, Front-end design tools and methodologies, Micro-architecture, Static-timing closure, Custom SoC ASIC products, Gate-level simulations, Block-level function verification, formal verification

Jenkins, Github, Git, Pytest, C, Verilog, Python, System Verilog, Git actions

Industry standard protocols, Gate level simulations, Power aware simulations, ARM based SoC verification, ASIC verification concepts

Register modeling, coverage analysis, firmware interaction, regression management, SERDES, Uvm, systemverilog, PHY architectures

Logic Design, Verilog, Sta, Synthesis, block and top-level timing constraints, Power product design, mixed signal integrated circuits, Scan Insertion, Timing Analysis, design constraints, ATPG generation, synthesis scripts, RTL Coding, micro-architecture, System-Verilog