Clp, Perl, Python, Tcl, Scan Insertion, Hybrid-TK Compression, SoC DFT Architecture, ATPG DRC analysis, P1500 implementation, Memory BIST implementation, JTAG BSCAN, MBIST, LEC, Bridging Cell-aware iddq fault models, iJTAG, Stuck at TDF, Logic and DRC analysis, Test coverage debug, ZERO delay and SDF based scan, LPCT, JTAG simulations, power analysis methodologies, LBIST

Arm, Python, RTL simulation, Debug, functional coverage closure, RISC-V, regression automation, x86 architecture, Uvm, SVA, systemverilog

Shell, Perl, Scripting, Tcl, debug methodologies, automation using Python, Uvm, assertion-based verification, systemverilog, regression frameworks, coverage closure, formal verification, Functional Verification

simulator , compiler , C, Verilog, Arm, Python, System Verilog, Embedded C Verification, Assembler, Floating point instructions implementation verification, RISC-V, Uvm, Logic Verification, processor toolchains, functional processor simulators

Perl scripting, C, Verilog, Python, Axi, Uvm, AHB, systemverilog