Senior/Staff Engineer, Design Verification

Renesas is a global semiconductor leader shaping the backbone of nextgeneration automotive, industrial, cloud, and IoT innovation. With over $9.3billion in annual revenue (2024) and a worldclass team of 22,700+ employees, Renesas operates at scale while retaining the agility to drive categorydefining breakthroughs. The company's footprint spans more than 30 countries, enabling deep customer proximity and a uniquely global innovative engine. As Japan's semiconductor powerhouse and a top global player in microcontrollers, analog, and power technologies, Renesas delivers realworld impact across EVs, smart factories, renewable energy infrastructure, and edge intelligence. For ambitious problemsolvers who want to work on meaningful, systemslevel challenges with huge industry leverage, Renesas offers the scale, stability, and strategic clarity of a market leader—paired with the transformative momentum of a company reinventing how the world computes, connects, and electrifies.

Renesas has a growing presence in India with HC approaching 1000+ and significant presence with active government and university collaboration as well as OSAT footprint (JV with CG India). With the growing importance of India as a market (Growing semiconductor market and government goals / mandates of localization needs) and talent hub, our division's (India for India) mission is to grow India market. We aspire to create products (SoCs, Software, Power and Analog chips etc) which serve needs for local market. Renesas is a leading electronics supplier globally, and this is a unique opportunity to directly influence the future products which will be offered to our customers in a new, fast growing and large Indian market with specific needs and applications.

• Be a part of endtoend verification execution for SOC owning complex digital IP's and subsystems from specification to signoff
• Define and drive IPlevel verification strategies, including test plans, coverage models, and closure criteria
• Develop scalable, reusable UVMbased verification environments for IP and subsystem verification
• Lead functional, code, assertion, and crosscoverage closure, ensuring highquality signoff with clear metrics
• Apply AI/MLassisted verification techniques to accelerate coverage convergence, identify stimulus gaps, and optimize regression efficiency
• Drive constraint random and directed test methodologies for thorough protocol, cornercase, and stress verification
• Collaborate with RTL, Architecture, Emulation, and SoC Verification teams to ensure seamless IP integration
• Review IP specifications and work with architects to translate requirements into robust verification plans and checkers
• Develop and deploy advanced checkers, scoreboards, assertions (SVA), and protocol monitors
• Work with EDA vendors to evaluate and adopt nextgeneration verification, coverage, and analytics tools
• Mentor junior engineers and promote bestinclass verification practices and continuous improvement
• Support GateLevel Simulation (GLS), lowpower verification, and postsilicon debug when required.
• Ensure IP deliverables meet quality, schedule, and reusability expectations for SoC integration.
  
  

• Bachelor's or master's degree in Electronics Engineering
• 2 - 8 years of experience in SoC Verification domains and have working knowledge of industry standard EDA toolkits.
• Strong expertise in UVMbased testbench architecture and development
• Proven experience in metricdriven verification, including functional and code coverage closure
• Deep understanding of SystemVerilog, UVM, assertions (SVA), and verification best practices
• Experience with directed and constrainedrandom verification methodologies
• Experience debugging complex design issues in simulation, emulation, and postsilicon environments
• Proficiency in Verilog/SystemVerilog, with working knowledge of C/C++, Shell scripting
• Strong analytical, problemsolving, and communication skills

Preferred/Plus Qualifications

• Handson experience using AI/MLbased verification tools for:
  • Coverage gap analysis
  • Test stimulus optimization
  • Regression triage and coverage acceleration
• Scripting expertise in Python, Perl, or TCL for automation and analytics
• Exposure to formal verification and hybrid formalsimulation flows
• Familiarity with highspeed or complex IPs, such as:
  • H.264
  • Security, debug, or safetycrititical
    
    

Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on worldleading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.

At Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.

We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.

Are you ready to join our team and shape the future with us

Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.