code coverage , Verilog, Debugging, FPGA Design, Scripting, Regression Testing, Vcs, systemverilog, Uvm, Testbench Development, Simulation Tools, Functional Verification, Timing Analysis, SoC Verification, Verification Plan, Verdi

Perl, Shell scripting, Python, vManager, Xcelium, Cadence environments, JasperGold, UVM methodologies

Tcl Scripting, System Verilog, Synopsys Mentor VIPs, verification methodologies, performance power optimization, random constraint-based testing, PCIe Gen3 Gen4 Gen5 Gen6, SMMU, Coresight architecture, Uvm, assertion-based verification, CHI protocols, UPF, Axi, formal verification, CXL 1.1 2.0 3.0, power-aware verification, coverage-driven testing, SVA

SystemVerilog Assertions (SVA), test environments , Gate-Level Simulation (GLS), Test Cases, Low power debug, Constrained-random verification environments, Uvm, systemverilog, Verification test benches, Formal tools, Verification methodologies, Coverage measures, formal verification

code coverage , perl, Regression Testing, Ovm, Ethernet Protocols, Python, multiple RTL simulators, X-propagation, Uvm, systemverilog, functional coverage

Python, C++, ASIC ASIC design, AI/ML, SoC EDA

Testplan, Perl, Verilog, Shell scripting, Python, System Verilog, testbench, Pre-silicon verification, Coverage Assertion writing, Uvm