Senior Staff Design Engineer

• Candidate will be responsible for building/maintaining highly configurable and reusable IO Subsystems (Note: An IO Subsystem is a logic IP that processes the IO Pads/IO Ring information and required logic to allow multiple on-chip peripherals to share the same IOs in a configurable manner)
• Candidate will be responsible forRTL designfor integration ofIO pads into SoC, building the required multiplexing logic and necessary power control signals integration.
• Strong fundamentals in DFT/Fault-grading and/or hands on experience.
• Significant Technical Contribution in to LogicIP/SoC Design&Architectural activities.
• Sound & Practical Written and Verbal Communication Skills.

Your Profile

You are best equipped for this task if you have:

• Must have worked in ASIC Design flow, with ASIC experience of 7 to 12years.
• Must be strong in scripting using Perl/Python
• Must be familiar with RTL design for ASIC development using Verilog.
• Must be familiar withLINT (LEDA/Spyglass),Clock-Domain-Crossing analysis, UPF, MVRC, Synthesis, Timing constraints and debugging STAreports.
• Strong mindset towards automation of repetitive work.
• Strong fundamentals inDFT/Fault-grading and/or hands on experience.
• Significant Technical Contribution intoLogic IP/SoCDesign &Architectural activities.
• Sound & Practical Written and Verbal Communication Skills.
• Moderate Individual Contributor with Freedom to Act, Team work and Learn